In the design and fabrication of integrated circuits, it is necessary to isolate adjacent active devices from one another so that leakage currents between devices do not cause the integrated circuits to fail or malfunction. As dimensions of semiconductor devices have shrunk, shallow trench isolation (STI) techniques have largely replaced other isolation techniques such as LOCOS. In fabricating an STI region, conventional photolithography and etching techniques may be used to create trenches in the integrated circuit substrate. The trenches may then be filled with one or more insulating materials, such as thermal silicon oxide. The wafer may then be planarized using chemical-mechanical polishing (CMP). Additional processing steps form the active devices on the substrate which are interconnected to create the circuitry in the integrated circuit.
As stated above, conventional photolithography techniques may be used to create trenches in the integrated circuit substrate. In photolithography, light may be used to expose a photolithography mask overlying the trench where the light may be reflected off of the integrated circuit layers underneath the mask. The reflections may have detrimental effects on the quality and accuracy of the resulting mask. To improve the results of photolithography at these small scales, SiN (SiON, SiRN) may be used as an anti-reflective coating or hard mask layer. The anti-reflective coating layer may reduce or substantially eliminate these reflections thereby resulting in improved masks for creating small features and structures in an integrated device.
After the formation of the gate, the hard mask/anti-reflective coating layer may need to be removed prior to subsequent device processing. The hard mask/anti-reflective coating layer may be removed using either a conventional wet strip process or a conventional plasma etching process. A conventional wet strip process may use hot phosphoric acid which may damage the polysilicon layer underlying the anti-reflective coating layer; whereas, a conventional plasma etching process may cause extensive gouging in any exposed field oxide, including in the thermal oxide in an STI region. Gouges in STI regions may alter the isolation properties of the STI region. Further, gouges in STI regions may create an uneven surface causing gap-fill problems for subsequent processing of the device wafer.
Therefore, there is a need in the art to strip a hard mask/anti-reflective coating layer that avoids damage to exposed polysilicon surfaces as well as avoids gouging exposed field oxide such as in STI regions.